HDI PWBs are characterized by high-density attributes including laser microvias, fine lines, smaller grid sizes and high performance thin materials. This increased density enables more functionality per unit area. Higher technology HDI PWBs have multiple layers of copper-filled, stacked microvias, which create a structure that enables even more complex interconnections. These very complex structures provide the necessary routing solutions for today's large pin-count chips utilized in mobile devices and other high technology products.
When it comes to HDI reliability of PWBs, what we must do is consider two parts: The copper interconnects and the base material. What one can do is test the reliability with thermal cycling using interconnect stress test (IST) coupons. The IST coupon tests the copper interconnection and checks for material damage. The coupon is fabricated on the production panel with the PWBs and has all the attributes of the PWB. So the coupon has the same construction, copper weights, hole sizes, grid sizes, and copper plating as is found in the corresponding board. The test thermal cycles the IST coupon, for typically 500 cycles, or until the coupon fails with a 10% increase in resistance due to cracks that develop in copper interconnections as a result of thermal cycling.
By measuring capacitance change between ground planes we can determine if there is any significant material damage in the coupon. What one does is to measure the capacitance in picofarads between adjacent ground planes before testing (to establish a base line), after preconditioning (a simulation of assembly and rework) and at the end of test. We then compare the measurement after preconditioning and at the end of test to those original readings. A -4% change or greater indicates significant material damage and a cross section is processed to confirm or refute this finding.
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